Microelectronic devices having conductive features, such as via plugs, metal lines, and the like, and methods for forming the devices are generally known. The conductive features of the microelectronic devices typically include conductive material, such as metal, and a barrier material, which barrier material typically reduces unwanted diffusion of the conductive material and promotes adhesion between the conductive material and the adjacent layers of the device.
The size of microelectronic devices, components, and features has decreased to increase device integration per unit area, reduce fabrication costs associated with the device, reduce signal delay time and the like. Consequently, the associated conductive features of the devices have also generally reduced in size. The reduced conductive feature size generally increases the current density through and resistance of the conductive feature. Increased current density through metal features may increase or cause electromigration, ie., the mass transport of metal due to the current flow. Electromigration may cause short circuits where the metal accumulates, opens where the metal has been depleted, or other device failures. Similarly, increased conductive feature resistance may cause unwanted device problems such as excess power consumption or heat generation. Therefore, materials with lower resistivity, which are also less susceptible to electromigration, are desirable.
Typical conductive materials used to form microelectronic conductive features include tungsten, aluminum, and aluminum alloys typically containing a small amount of copper. Recently, however, materials such as copper, which have lower resistivity and are more resistant to electromigration than tungsten, alumninum, and aluminum alloys, have been proposed as alternate conductive materials in microelectronic fabrication.
Although conductive features including copper or similar materials are generally advantageous because they may have lower resistance and may be less susceptible to electromigration for a given feature size, these conductive features may suffer from several shortcomings. For example, conductive features including copper may be relatively difficult to form using conventional microelectronic device fabrication techniques. In particular, copper is relatively difficult to etch using now known wet or dry processes because it does not readily form soluble or volatile compounds when exposed to conventional etching reactants. Consequently, conductive features including copper are typically formed using damascene processing, wherein the feature is formed by creating trenches or vias on the wafer surface, depositing material onto the wafer surface and into trenches and vias, and removing the material from the top surface of the wafer, leaving trenches and vias filled with conductive material. If the conductive feature also includes barrier material, the barrier material may be deposited onto the wafer surface prior to conductive material deposition, and removed from the wafer surface subsequent to conductive material removal from the surface.
Copper features formed in accordance with prior art techniques may also be disadvantageous because copper diffuses relatively rapidly through typical barrier layers used in microelectronic fabrication, such as titanium or combinations of titanium and titanium nitride, and other device layers such as silicon and oxides and nitrides thereof. In addition, copper may degrade electrical performance or cause current leakage between interconnect features or in the microelectronic device if the copper diffuses to active areas of the device. Consequently, features formed of copper and the like may require relatively thick layers of titanium, titanium nitride, or combinations thereof to prevent the diffusion of copper to other device regions. Relatively thick barrier layers may negate most if not all of the advantages associated with using low resistivity conductive material because, in part, the barrier layer typically has higher resistivity than the copper, and the effective resistance of the conductive feature typically increases as the barrier material film thickness increases. Nevertheless, titanium-based diffusion barriers are often used in device fabrication-because the films are relatively easy to remove using standard copper chemical mechanical polishing processes and these layers provide adequate adhesion between the conductive material and the wafer surface.
Alternative diffusion barrier layers such as those formed from tantalum, tantalum nitride, and the like, may also be used to prevent or reduce diffusion of copper or similar materials. Generally, these materials are more resistant to copper diffusion than the titanium-based layers (for a given thickness). However, the tantalum films are generally more difficult to remove from the surface of the wafer than the titanium-based layers. In particular, copper chemical mechanical polishing processes generally remove copper and titanium-based films at a rate which is typically greater than the rate of tantalum removal. Consequently, as tantalum is removed from the wafer surface, copper material below the surface of the wafer (e.g. in the vias and trenches) is often removed, causing dishing in the copper features. The dishing of the copper features may deleteriously affect the performance of the microelectronic device, because the amount of copper in the via or trench determines the effective feature cross section for current flow. As the effective cross section decreases, the current density and resistance of the feature generally increase.
In addition, because tantalum is difficult to remove from the surface of the wafer using typical copper chemical mechanical polishing processes, an aggressive polishing process may be employed to remove the tantalum. The aggressive process may cause unwanted scratching and erosion of dielectric or other films on the surface of the wafer.
To reduce the amount of dishing and scratching that occurs during the last phase of CMP (over polishing), a two-step polishing process may be used to remove the conductive and barrier layers, respectively. In particular, a first polishing step, which removes the conductive material at a relatively high rate, may be used to remove most of the conductive material and a second polishing step, which removes tantalum at a relatively high rate and conductive material at a relatively low rate, may be used to remove the barrier layer on the wafer surface. However, two-step processes generally add complexity and increase wafer fabrication and device costs.
Therefore, microelectronic conductive features that overcome the shortcoming of prior art conductive features and methods for forming the features are desired. In particular, conductive features with low resistivity and high resistance to electromigration, which are relatively easy and inexpensive to manufacture are desired.